TheZestET2-J是一款简单易用的FPGA板，它采用XilinxArtix-7可编程FPGA已一个性能非常高的TCP/IP减负引擎(TOE)芯片.,用于数据流高速处理以及数据采集和控制。ZestET2-J以太网FPGA板采用XilinxArtix-7,及高性能TCP/IP减负引擎TheZestET2-J是一款简单易用的FPGA板，它采用XilinxArtix-7可编程FPGA已一个性能非常高的TCP/IP减负引擎(TOE)芯片.,用于数据流高速处理以及数据采集和控制。ZestET2-JEthernetFPGABoardTheZestET2-JisaneasytouseFPGAboardwithXilinxArtix-7userprogrammableFPGAandaveryhighperformanceTCP/IPOffloadEngine(TOE)chip.Theboardcanbeusedasaprogrammableinterfacetoexternaldevices,forhighspeedprocessingofstreamingdata,andfordataacquisitionandcontrol.Itprovidesasimplebridgebetweenahighspeedcomputernetworkandaprogrammabledigitalinterface.TheTOEsustainsadatarateover100MBytes/sineachdirectionandincludesauserprogrammableCPUforoptionalhigherlevelprotocols.OrangeTree&＃39;sproprietaryGigExpeditechip"GigEx"isaTOEthathandlesalltheEthernetcommunicati***protocols.Thisle***estheArtix-7FPGAcompletelyfreefortheuser&＃39;sapplication,andmeanstheuserdoesnotrequireanyknowledgeofEthernetprotocols.WiththemainprocessingengineimplementedinTOEha***are,sustaineddataratesover100MBytes/secareachieved.ThethirdgenerationofOrangeTree’scustomGigExchipprovidesauser-programmableCPU.Thisiscompletelyfreefortheusertoprogram,forexamplewithhigherlevelEthernetprotocolssuchasGigEVisionandIndustrialEthernet,oritcanbeleftunprogrammed.YoucanreadmoreaboutGigExhere.Withitscompactformfactor(40mmx67mm),theboardisideallysuitedtointegrationinembeddedsystemsandOEMequipment.ItfeaturesauserprogrammableXilinxArtix-7FPGAcoupledwith512MBytesofhighspeedDDR3memory.TheFPGAcanbeprogrammedfromon-boardFlash,EthernetorJTAG.Forevaluationtherearetwobreakoutboa******ailable:ZestET2-J-BRK-HsimplyconnectstheUserFPGAIOpinstofour0.1”pitchheaders.ItalsohasthestandardXilinxJTAGheaderfortheZestET2-JUserFPGA.ZestET2-J-BRK-FconnectstheUserFPGAIOpinstoanFMCconnectoranda0.1”pitchheader.ItincludesallpowersuppliesfortheZestET2-JandtheFMCandispoweredfrom12V.ItalsohasthestandardXilinxJTAGheaderfortheZestET2-JUserFPGAandtheFMC.BenefitsEasytousewithnodetailednetworkingknowledgerequiredOfferssimpleaccesstoveryfastdataratesoverGigabitEthernetwithouth***ingtointegratecomplexnetworkingha***areandsoftwareDevicesconnectedtoUserFPGAcancommunicateviaEthernetwithoutusingaprocessororincurringprocessoroverheadsVirtuallynoFPGAresourcesusedfornetworkcommunicati***,somostofFPGA***ailablefordataprocessingCanbeextendedtoapplicationlayerprotocolsrunningaboveTCPorUDPeitherinUserCPUorUserFPGAPlugandplayEthernetStandalonedesktoporbenchtopuseFeaturesMorethan100MBytes/secsustaineddatarateineachdirectionoverGigabitEthernetXilinxArtix-7UserFPGAand512MBytesDDR3memory105UserIOpinsGigExha***areTOEforUDPandTCP/IPoffloadUserCPUwithintheGigExTOEforuserdefinedapplicationlayerprotocols(orcanbeleftunprogrammed)Real-timeEthernetextensi***PrecisionTimeProtocol(PTP)andSynchronousEthernet(SyncE)SinglepowersupplyandpowerjackRJ45EthernetjackFreeWindowstoolsbasedonGCCandEclipsefortheGigExUserCPUFreetools***ailablefromXilinxforcreatingFPGAdesigns(Webpack)WindowsandLinuxsoftwaresupportforconfiguringandcommunicatingwiththeUserFPGALogiccoresforallFPGAinterfacesReferencedesigns(includingC,VHDLandVerilogsource)ZestDAQframeworkoflogiccoresandhostsoftwareforquickimplementationofdataacquisitionandcontrolapplicati***)