CYPRESS中国区***（香港齐芯科技有限公司）CY7C64713-128AXC特点:功能描述CY7C64713-128AXC是一个全静态设计，支持时钟频率高达350兆赫。产生的信号和retimed片上，以确保四个输出***的***低偏移。两个***的LVPECL兼容的时钟输入提供。此功能支持冗余差分时钟源。此外，CY7C64713-128AXC支持单端的LVCMOS时钟分配系统。四个输出***每一个都可以单独提供的2.5V或3.3V，支持混合电压应用。选择的FSELx引脚之间的输入参考频率划分由一个或两个。该分频器可设置为每个单独的输出***。在CY7C64713-128AXC输出***在highCimpedance状态解除报警的温仁才由引脚。声称将在温仁才使输出***。请参阅第4页的详细信息，输出HighCImpedance控制表。输出可同步停止（逻辑低状态）。提供的产出能力的LVCMOS兼容程度，推动终止50Ω传输线路。对于系列终止输电线路，对CY7C64713-128AXC输出每个人都可以驱动一个或两个痕迹给予了1:32的设备在VCC=3.3V的有效扇出。该器件采用7x7平方毫米封装，48引脚LQFP封装。CY7C64713-128AXC(***)***大额定值:手动复位输入许多微处理器为基础的产品需要手动复位capabil知音，使运营商，测试技术人员，或外部逻辑电路来启动复位。甲先生为逻辑低，serts复位。虽然他仍然断言复位低，主动为复位超时周期（激进党）致辞后返回高。这种输入有一个内部20kΩ的上拉电阻，因此它可以在公开，如果不使用它。议员可驱动具有TTL或CMOS逻辑电平，或开漏/集电极输出。连接一个常开的MR瞬时开关至GND，以创造一个手动复位功能，外部去抖电路不需要。如果议员是由长电缆或驱动装置是用在嘈杂的环境，从议员连接0.1μF电容到地提供了额外的噪声***力。CY7C64713-128AXC引脚说明:完整的闭环电流控制的同步旋转磁场定向帧（使用转子角观察员）闭环速度控制速度估计可配置参数（PI控制器的收益，有价证券***限额范围内输出，电流反馈扩大器，PWM载波频率为基础计算）为适应不同永磁电机内置为启动传感器控制逻辑，斜坡，在启动和运行与配置的转矩电流限制，条件自动重试（可编程）模拟参考输入（可用于高速参考）RS232C/RS422参考输入全部动态制动直流母线电压的限制逐周期控制开/关控制制动IGBT的损失***小化空间矢量PWM的死区时间插入内建两个IR2175电***应IC接口相损耗，过流（GATEKILL输入），过压，欠压，***保护低成本串行12位A/D转换接口与复用器和样品/保持电路可选逆变腿（偏低）在IR2175电***应集成电路代替4路模拟输出（脉宽调制）对内部数据的EEPROM启动初始化本地/通过主机参数寄存器接口AT24C01A，128X8通用主机通信接口RS232C或RS422主机接口快速SPI从主机接口与多点能力的并行主机接口（共12针）复用数据/地址总线地址使能研发/西铁离散I/O，以***模式运作STARTSTOP（输入）埃斯托普（输入）CY7C64713-128AXCFeatures:FunctionalDescriptionTheCY7C64713-128AXCisafullstaticdesignsupportingclockfrequenciesupto350MHz.Thesignalsaregeneratedandretimedon-chiptoensureminimalskewbetweenthefouroutputbanks.TwoindependentLVPECLcompatibleclockinputsare***ailable.Thisfeaturesupportsredundantdifferentialclocksources.Inaddition,theCY7C64713-128AXCsupportssingle-endedLVCMOSclockdistributionsystems.Eachofthefouroutputbankscanbeindividuallysuppliedby2.5Vor3.3V,supportingmixedvoltageapplicati***.TheFSELxpinschoosebetweendivisionoftheinputreferencefrequencybyoneortwo.Thefrequencydividercanbesetindividuallyforeachoutputbank.TheCY7C64713-128AXCoutputbanksareinhighCimpedancestatebydeassertingtheOENpins.AssertingOENwilltheenableoutputbanks.PleaseseetheOutputHighCImpedanceControltableonpage4fordetails.Theoutputscanbesynchronouslystopped(logiclowstate).TheoutputsprovideLVCMOScompatiblelevelswiththecapabilitytodriveterminated50Ωtran***issionlines.Forseriesterminatedtran***issionlines,eachoftheCY7C64713-128AXCoutputscandriveoneortwotracesgivingthedevicesaneffectivefanoutof1:32atVCC=3.3V.Thedeviceispackagedina7x7mm248-leadLQFPpackage.CY7C64713-128AXC(Absolute)MaximumRatings:ManualResetInputManyµP-basedproductsrequiremanualresetcapabil-ity,allowingtheoperator,atesttechnician,orexternallogiccircuitrytoinitiateareset.AlogiclowonMRas-sertsreset.ResetremainsassertedwhileMRislow,andfortheResetActiveTimeoutPeriod(tRP)afterMRreturnshigh.Thisinputhasaninternal20kΩpull-upresistor,soitcanbeleftopenifitisnotused.MRcanbedrivenwithTTLorCMOS-logiclevels,orwithopen-drain/collectoroutputs.ConnectanormallyopenmomentaryswitchfromMRtoGNDtocreateamanual-resetfunction;externaldebouncecircuitryisnotrequired.IfMRisdrivenfromlongcablesorifthedeviceisusedinanoisyenvironment,connectinga0.1µFcapacitorfromMRtogroundprovidesadditionalnoiseimmunity.CY7C64713-128AXCPinout:CompleteclosedloopcurrentcontrolbasedonSynchronouslyRotatingFrameFieldOrientation(usingRotorAngleObserver)ClosedloopvelocitycontrolbasedonestimatedspeedConfigurableparameters(PIcontrollergains,PIoutputlimitrange,currentfeedbackscaling,PWMcarrierfrequency)provideadaptationtovariousPMmotorsBuilt-inSensorlesscontrollogicforstart-up,ramping,andrunningconditi***AutoRetry(programmable)onstart-upwithconfigurabletorquecurrentlimitAnalogreferenceinput(canbeusedforspeedreference)RS232C/RS422referenceinputFulldynamicbrakingcontrolforDCbusvoltagelimitationCycle-by-cycleon/offControlforBrakeIGBTLossminimizationSpaceVectorPWMwithdeadtimeinsertionBuild-intwoIR2175currentsensingICinterfacesPhaseLoss,Overcurrent(GATEKILLinput),Overvoltage,Undervoltage,OverspeedprotectionLowcostserial12bitA/Dinterfacewithmultiplexerandsample/holdcircuitOptionalInverterLeg(lowside)currentsensinginlieuofIR2175IC4channelanalogoutput(PWM)LocalEEPROMforstartupinitializationofinternaldata/parametersthroughhostregisterinterfaceAT24C01A,128X8VersatilehostcommunicationinterfaceRS232CorRS422hostinterfaceFastSPIsl***ehostinterfacewithmulti-dropcapabilityParallelHostinterface(total12pins)Multiplexeddata/addressbusAddressEnableRD/WRDiscreteI/OsforStandalonemodeoperationSTARTSTOP(Input)ESTOP(Input))