TheSpartan®-6familyprovidesleadingsystemintegrationcapabilitieswiththelowesttotalcostforhigh-volumeapplicati***.Thethirteen-memberfamilydeliversexpandeddensitiesrangingfromto147,443logiccells,withhalfthepowerc***umptionofpreviousSpartanfamilies,andfaster,morecomprehensiveconnectivity.Builtonamature45nmlow-powercopperprocesstechnologythatdeliverstheoptimalbalanceofcost,power,andperformance,theSpartan-6familyoffersanew,moreefficient,dual-register6-inputlookuptable(LUT)logicandarichselectionofbuilt-insystem-levelblocks.Theseincludex9Kb)blockRAMs,secondgenerationDSP48A1slices,SDRAMmemorycontrollers,enhancedmixed-modeclockmanagementblocks,SelectIOTMtechnology,poweroptimizedhigh-speedserialtransceiverblocks,PCIExpress®compatibleEndpointblocks,advancedsystem-levelpowermanagementmodes,auto-detectconfigurationopti***,andenhancedIPsecuritywithAESandDeviceDNAprotection.ThesefeaturesprovidealowcostprogrammablealternativetocustomASICproductswithunprecedentedeaseofuse.Spartan-6FPGAsofferthebestsolutionforhigh-volumelogicdesigns,c***umer-orientedDSPdesigns,andcost-sensitiveembeddedapplicati***.Spartan-6FPGAsaretheprogrammablesiliconfoundationforTargetedDesignPlatformsthatdeliverintegratedsoftwareandha***arecomponentsthatenabledesignerstofocusoninnovationassoonastheirdevelopmentcyclebegins.Spartan-6Family:Spartan-6LXFPGA:LogicoptimizedSpartan-6LXTFPGA:High-speedserialconnectivityDesignedforlowcostMultipleefficientintegratedblocksOptimizedselectionofI/Ostanda***StaggeredpadsHigh-volumeplasticwire-bondedpackagesLowstaticanddynamicpower45nmprocessoptimizedforcostandlowpowerHibernatepower-downmodeforzeropowerSuspendmodemaintainsstateandconfigurationwithmulti-pinwake-up,controlenhancementLower-power1.0Vcorevoltage(LXFPGAs,-1Lonly)Highperformance1.2Vcorevoltage(LXandLXTFPGAs,-2,-3,and-3Nspeedgrades)Multi-voltage,multi-standardSelectIOTMinterfacebanksto1,080Mb/sdatatransferrateperdifferentialI/OSelectableoutputdrive,24mAperpinto1.2VI/Ostanda***andprotocolsLow-costHSTLandSSTLmemoryinterfacesHotswapcomplianceAdjustableI/OslewratestoimprovesignalintegrityHigh-speedGTPserialtransceiversintheLXTFPGAsto3.2Gb/sHigh-speedinterfacesincluding:SerialATA,Aurora,1GEthernet,PCIExpress,OBSAI,CPRI,EPON,GPON,DisplayPort,andXAUIIntegratedEndpointblockforPCIExpressdesigns(LXT)Low-costPCI®technologysupportcompatiblewiththe33MHz,32-and64-bitspecification.EfficientDSP48A1slicesHigh-performancearithmeticandsignalprocessingFastx18multiplierand48-bitaccumulatorPipeliningandcascadingcapabilityPre-addertoassistfilterapplicati***IntegratedMemoryControllerblocksDDR,DDR2,DDR3,andLPDDRsupportDataratesto800Mb/s(12.8Gb/speakbandwidth)Multi-portbusstructurewithindependentFIFOtoreducedesigntimingissuesAbundantlogicresourceswithincreasedlogiccapacityOptionalshiftregisterordistributedRAMsupportEfficient6-inputLUTsimproveperformanceandminimizepowerLUTwithdualflip-flopsforpipelinecentricapplicati***BlockRAMwithawiderangeofgranularityFastblockRAMwithbytewriteenable18Kbblocksthatcanbeoptionallyprogrammedastwoindependent9KbblockRAMsClockManagementTile(CMT)forenhancedperformanceLownoise,flexibleclockingDigitalClockManagers(DCMs)eliminateclockskewanddutycycledistortionPhase-LockedLoops(PLLs)forlow-jitterclockingFrequencysynthesiswithsimultaneousmultiplication,division,andphaseshiftingSixteenlow-skewglobalclocknetworksSimplifiedconfiguration,supportslow-coststanda***2-pinauto-detectconfigurationBroadthird-partySPI(uptox4)andNORflashsupportFeaturerichXilinxPlatformFlashwithJTAGMultiBootsupportforremoteupgradewithmultiplebitstreams,usingwatchdogprotectionEnhancedsecurityfordesignprotectionUniqueDeviceDNAidentifierfordesignauthenticationAESbitstreamencryptioninthelargerdevicesFasterembeddedprocessingwithenhanced,lowcost,MicroBlazeTMsoftprocessorIndustry-leadingIPandreferencedesigns©2009­2011Xilinx,Inc.Xilinx,theXilinxlogo,Artix,ISE,Kintex,Spartan,Virtex,Zynq,andotherdesignatedbrandsincludedhereinaretrademarksofXilinxintheUnitedStatesandothercountries.PCI,PCIeandPCIExpressaretrademarksofPCI-SIGandusedunderlicense.Allothertrademarksarethepropertyoftheirrespectiveowners.ConfigurableLogicBlocks(CLBs)DeviceLogicCells(1)Slices(2)MaxFlip-FlopsDistributedRAM(Kb)DSP48A1Slices(3)BlockRAMBlocksKb(4)CMTs(5)Max(Kb)MemoryEndpointMaximumTotalMaxControllerBlocksforGTPI/OUserBlocksPCIExpressTransceiversBanksI/O(Max)(6)Spartan-6FPGAlogiccellratingsreflecttheincreasedlogiccellcapabilityofferedbythenew6-inputLUTarchitecture.EachSpartan-6FPGAslicecontainsfourLUTsandeightflip-flops.EachDSP48A1slicecontainsx18multiplier,anadder,andanaccumulator.BlockRAMsarefundamentallyKbinsize.Eachblockcanalsobeusedastwoindependent9Kbblocks.EachCMTcontainstwoDCMsandonePLL.MemoryControllerBlocksarenotsupportedinthe-3Nspeedgrade.Spartan-6FPGApackagecombinati***withthe***ailableI/OsandGTPtransceiversperpackageareshowninTable2.Duetothetransceivers,theLXandLXTpinoutsarenotcompatible.Table2:Spartan-6Device-PackageCombinati***andMaximum***ailableI/OsPackageBodySize(mm)Pitch(mm)Device8x80.5Notes:1.Thereisnomemorycontrolleronthedevicesinthesepackages.2.Memorycontrollerblocksupportx8ontheXC6SLX9andXC6SLX16devicesintheCSG225package.ThereisnomemorycontrollerintheXC6SLX4.3.Thesedevicesare***ailableinbothPbandPb-free(additionalG)packagesasstandardorderingopti***.4.ThesepackagessupporttwoofthefourmemorycontrollersintheXC6SLX100T,XC6SLX150,andXC6SLX150Tdevices.Spartan-6FPGAsstorethecustomizedconfigurationdatainSRAM-typeinternallatches.Thenumberofconfigurationbitsisbetween3Mband33Mbdependingondevicesizeanduser-designimplementationopti***.TheconfigurationstorageisvolatileandmustbereloadedwhenevertheFPGAispoweredup.ThisstoragecanalsobereloadedatanytimebypullingthePROGRAM_BpinLow.Severalmethodsanddataformatsforloadingconfigurationare***ailable.Bit-serialconfigurati***canbeeithermasterserialmode,wheretheFPGAgeneratestheconfigurationclock(CCLK)signal,orsl***eserialmode,wheretheexternalconfigurationdatasourcealsoclockstheFPGA.Forbyte-wideconfigurati***,masterSelectMAPmodegeneratestheCCLKsignalwhilesl***eSelectMAPmodereceivestheCCLKsignalforthe8-and16-bit-widetransfer.Inmasterserialmode,thebeginningofthebitstreamcanoptionallyswitchtheclockingsourcetoanexternalclock,whichcanbefasterormoreprecisethantheinternalclock.The***ailableJTAGpinsuseboundary-scanprotocolstoloadbit-serialconfigurationdata.)